//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 141732
// File Date           :  2012-12-05 16:55:57 +0000 (Wed, 05 Dec 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA interface block slave domain
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                        nic400_ib_chiplink_slv_axi4_tpv_ib_slave_domain_ysyx_rv32.v
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//  Slave domain of AMBA Interface Block (IB) 'chiplink_slv_axi4_tpv_ib'.
//
//  This IB is a component of AMIB named chiplink_slv_axi4_tpv
//  
//  32bit to 64bit upsize
//
//           SIF prot axi4
//           MIF prot axi4
//           SIF DW   32
//           MIF DW   64
//
//           MIF  axi4_m
//           RIF  axi_r
//           IIF  axi_r
//           BIF  bif
//
//           Burstbreak  = false
//
//------------------------------------------------------------------------------

`include "nic400_ib_chiplink_slv_axi4_tpv_ib_defs_ysyx_rv32.v"
`include "Axi.v"

module nic400_ib_chiplink_slv_axi4_tpv_ib_slave_domain_ysyx_rv32
  (
  
    //axi4_s AXI bus

    //AW Channel
    awid_axi4_s,
    awaddr_axi4_s,
    awlen_axi4_s,
    awsize_axi4_s,
    awburst_axi4_s,
    awlock_axi4_s,
    awcache_axi4_s,
    awprot_axi4_s,
    awvalid_axi4_s,
    awregion_axi4_s,
    awready_axi4_s,

    //W Channel
    wdata_axi4_s,
    wstrb_axi4_s,
    wlast_axi4_s,
    wvalid_axi4_s,
    wready_axi4_s,

    //B Channel
    bid_axi4_s,
    bresp_axi4_s,
    bvalid_axi4_s,
    bready_axi4_s,

    //AR Channel
    arid_axi4_s,
    araddr_axi4_s,
    arlen_axi4_s,
    arsize_axi4_s,
    arburst_axi4_s,
    arlock_axi4_s,
    arcache_axi4_s,
    arprot_axi4_s,
    arvalid_axi4_s,
    arregion_axi4_s,
    arready_axi4_s,

    //R Channel
    rid_axi4_s,
    rdata_axi4_s,
    rresp_axi4_s,
    rlast_axi4_s,
    rvalid_axi4_s,
    rready_axi4_s,

    //Inter-domain IB bus

    //AW Inter-domain bus
    aw_data_async,
    aw_rpntr_gry_async,
    aw_rpntr_bin,
    aw_wpntr_gry_async,

    //B Inter-domain bus
    b_data_async,
    b_rpntr_gry_async,
    b_rpntr_bin,
    b_wpntr_gry_async,

    //AR Inter-domain bus
    ar_data_async,
    ar_rpntr_gry_async,
    ar_rpntr_bin,
    ar_wpntr_gry_async,

    //R Inter-domain bus
    r_data_async,
    r_rpntr_gry_async,
    r_rpntr_bin,
    r_wpntr_gry_async,

    //W Inter-domain bus
    w_data_async,
    w_rpntr_gry_async,
    w_rpntr_bin,
    w_wpntr_gry_async,

    //Clock and reset signals
    aclk_s,
    aresetn_s

  );



  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //axi4_s AXI bus


  //AW Channel
  input   [3:0]       awid_axi4_s;             //write id of axi4_s AXI bus AW channel
  input   [31:0]      awaddr_axi4_s;           //write address of axi4_s AXI bus AW channel
  input   [7:0]       awlen_axi4_s;            //write length field of axi4_s AXI bus AW channel
  input   [2:0]       awsize_axi4_s;           //write size of axi4_s AXI bus AW channel
  input   [1:0]       awburst_axi4_s;          //write burst length of axi4_s AXI bus AW channel
  input               awlock_axi4_s;           //write lock of axi4_s AXI bus AW channel
  input   [3:0]       awcache_axi4_s;          //write cache field of axi4_s AXI bus AW channel
  input   [2:0]       awprot_axi4_s;           //write prot field of axi4_s AXI bus AW channel
  input               awvalid_axi4_s;          //write valid of axi4_s AXI bus AW channel
  input   [3:0]       awregion_axi4_s;         //write region selection signal
  output              awready_axi4_s;          //write ready of axi4_s AXI bus AW channel

  //W Channel
  input   [31:0]      wdata_axi4_s;            //write data of axi4_s AXI bus W Channel
  input   [3:0]       wstrb_axi4_s;            //write strobes of axi4_s AXI bus W Channel
  input               wlast_axi4_s;            //write last of axi4_s AXI bus W Channel
  input               wvalid_axi4_s;           //write valid of axi4_s AXI bus W Channel
  output              wready_axi4_s;           //write ready of axi4_s AXI bus W Channel

  //B Channel
  output  [3:0]       bid_axi4_s;              //b response id of axi4_s AXI bus B Channel
  output  [1:0]       bresp_axi4_s;            //b response status of axi4_s AXI bus B Channel
  output              bvalid_axi4_s;           //b response valid of axi4_s AXI bus B Channel
  input               bready_axi4_s;           //b response ready of axi4_s AXI bus B Channel

  //AR Channel
  input   [3:0]       arid_axi4_s;             //read id of axi4_s AXI bus AR Channel
  input   [31:0]      araddr_axi4_s;           //read address of axi4_s AXI bus AR Channel
  input   [7:0]       arlen_axi4_s;            //read length of axi4_s AXI bus AR Channel
  input   [2:0]       arsize_axi4_s;           //read size of axi4_s AXI bus AR Channel
  input   [1:0]       arburst_axi4_s;          //read burst length of axi4_s AXI bus AR Channel
  input               arlock_axi4_s;           //read lock of axi4_s AXI bus AR Channel
  input   [3:0]       arcache_axi4_s;          //read cache field of axi4_s AXI bus AR Channel
  input   [2:0]       arprot_axi4_s;           //read prot field of axi4_s AXI bus AR Channel
  input               arvalid_axi4_s;          //read valid of axi4_s AXI bus AR Channel
  input   [3:0]       arregion_axi4_s;         //read region selection signal
  output              arready_axi4_s;          //read ready of axi4_s AXI bus AR Channel

  //R Channel
  output  [3:0]       rid_axi4_s;              //read id of axi4_s AXI bus R Channel
  output  [31:0]      rdata_axi4_s;            //read data of axi4_s AXI bus R Channel
  output  [1:0]       rresp_axi4_s;            //read response status of axi4_s AXI bus R Channel
  output              rlast_axi4_s;            //read last of axi4_s AXI bus R Channel
  output              rvalid_axi4_s;           //read valid of axi4_s AXI bus R Channel
  input               rready_axi4_s;           //read ready of axi4_s AXI bus R Channel

  //Inter-domain IB bus


  //AW Inter-domain bus
  output  [60:0]      aw_data_async;           //AW Channel Data
  input   [1:0]       aw_rpntr_gry_async;      //AW Channel Read Pointer (GRY)
  input               aw_rpntr_bin;            //AW Channel Read Pointer (BIN) for data mux
  output  [1:0]       aw_wpntr_gry_async;      //AW Channel Read Pointer (GRY)

  //B Inter-domain bus
  input   [5:0]       b_data_async;            //B Channel Data
  output  [1:0]       b_rpntr_gry_async;       //B Channel Read Pointer (GRY)
  output              b_rpntr_bin;             //B Channel Read Pointer (BIN) for data mux
  input   [1:0]       b_wpntr_gry_async;       //B Channel Read Pointer (GRY)

  //AR Inter-domain bus
  output  [60:0]      ar_data_async;           //AR Channel Data
  input   [1:0]       ar_rpntr_gry_async;      //AR Channel Read Pointer (GRY)
  input               ar_rpntr_bin;            //AR Channel Read Pointer (BIN) for data mux
  output  [1:0]       ar_wpntr_gry_async;      //AR Channel Read Pointer (GRY)

  //R Inter-domain bus
  input   [70:0]      r_data_async;            //R Channel Data
  output  [1:0]       r_rpntr_gry_async;       //R Channel Read Pointer (GRY)
  output              r_rpntr_bin;             //R Channel Read Pointer (BIN) for data mux
  input   [1:0]       r_wpntr_gry_async;       //R Channel Read Pointer (GRY)

  //W Inter-domain bus
  output  [72:0]      w_data_async;            //W Channel Data
  input   [1:0]       w_rpntr_gry_async;       //W Channel Read Pointer (GRY)
  input               w_rpntr_bin;             //W Channel Read Pointer (BIN) for data mux
  output  [1:0]       w_wpntr_gry_async;       //W Channel Read Pointer (GRY)

  //Clock and reset signals
  input               aclk_s;                  //main clock
  input               aresetn_s;               //main reset
   

  // ---------------------------------------------------------------------------
  // Internal signals
  // ---------------------------------------------------------------------------

  // AW Channel wires at boundary
  
  wire                aw_boundary_src_valid;
  wire                aw_boundary_src_ready;

  wire [60:0]         aw_boundary_src_data;     // concatenation of the inputs
  wire [60:0]         aw_boundary_dst_data;     // concatenation of the registered inputs


  // AR Channel wires at boundary
  
  wire                ar_boundary_src_valid;
  wire                ar_boundary_src_ready;

  wire [60:0]         ar_boundary_src_data;     // concatenation of the inputs
  wire [60:0]         ar_boundary_dst_data;     // concatenation of the registered inputs


  // R Channel wires at boundary
  
  wire                r_boundary_dst_valid;
  wire                r_boundary_dst_ready;

  wire [70:0]         r_boundary_dst_data;     // concatenation of the registered inputs


  // W Channel wires at boundary
  
  wire                w_boundary_src_valid;
  wire                w_boundary_src_ready;

  wire [72:0]         w_boundary_src_data;     // concatenation of the inputs
  wire [72:0]         w_boundary_dst_data;     // concatenation of the registered inputs


  // B Channel wires at boundary
  
  wire                b_boundary_dst_valid;
  wire                b_boundary_dst_ready;

  wire [5:0]          b_boundary_dst_data;     // concatenation of the registered inputs


  // AW Channel wires at slave_port
  
  wire [60:0]         aw_slave_port_src_data;     // concatenation of the inputs
  wire [60:0]         aw_slave_port_dst_data;     // concatenation of the registered inputs

  wire                aw_slave_port_dst_valid;
  wire                aw_slave_port_dst_ready;
  wire                aw_slave_port_src_valid;
  wire                aw_slave_port_src_ready;

  // AR Channel wires at slave_port
  
  wire [60:0]         ar_slave_port_src_data;     // concatenation of the inputs
  wire [60:0]         ar_slave_port_dst_data;     // concatenation of the registered inputs

  wire                ar_slave_port_dst_valid;
  wire                ar_slave_port_dst_ready;
  wire                ar_slave_port_src_valid;
  wire                ar_slave_port_src_ready;

  wire [38:0]         r_slave_port_src_data;     // concatenation of the inputs
  wire [38:0]         r_slave_port_dst_data;     // concatenation of the registered inputs

  wire [36:0]         w_slave_port_src_data;     // concatenation of the inputs
  wire [36:0]         w_slave_port_dst_data;     // concatenation of the registered inputs

  wire [5:0]          b_slave_port_src_data;     // concatenation of the inputs
  wire [5:0]          b_slave_port_dst_data;     // concatenation of the registered inputs

  wire [1:0]          aw_rpntr_gry_async;            // gray encoded rd-pointer for AW channel
  wire                aw_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          aw_wpntr_gry_async;            // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          ar_rpntr_gry_async;            // gray encoded rd-pointer for AR channel
  wire                ar_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          ar_wpntr_gry_async;            // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          w_rpntr_gry_async;             // gray encoded rd-pointer for W channel
  wire                w_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          w_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          b_rpntr_gry_async;             // gray encoded rd-pointer for B channel
  wire                b_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          b_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          r_rpntr_gry_async;             // gray encoded rd-pointer for R channel
  wire                r_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          r_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc
  

  //------------------------------------------------------------------------------
  // Wires that run between blocks
  //------------------------------------------------------------------------------

  //Signals between write address format and B channel
  wire [4:0]          bdata_data;
  wire                bdata_valid;
  wire                bdata_ready;

  //Signals between the AW Format Block and the Write Control Block
  wire [15:0]         awdata_data;
  wire                awdata_valid;
  wire                awdata_ready;

  //Signals between write_control and merge buffer
  wire                merge;
  wire                merge_clear;
  wire [1:0]          data_select;
  wire                strb_skid_valid;

  //Signals from the merge buffer to the write_contol block
  wire [63:0]         wdata_merged;
  wire [7:0]          wstrb_merged;
  //Signals bewteen read address format and CAM Slices
  wire [18:0]         arfifo_data;
  wire                arfifo_valid;
  wire                arfifo_ready;  
  wire  [60:0]       aw_fmt_src_data;
  wire  [60:0]       ar_fmt_src_data;
  wire  [60:0]       aw_fmt_dst_data;
  wire  [60:0]       ar_fmt_dst_data;

  // AXI_bif BIF



  // AW Channel: Connections between AW format block and boundary
  wire [3:0]          awid_bif;
  wire [31:0]         awaddr_bif;
  wire [7:0]          awlen_bif;
  wire [2:0]          awsize_bif;
  wire [1:0]          awburst_bif;
  wire           awlock_bif;
  wire [3:0]          awcache_bif;
  wire [2:0]          awprot_bif;
  wire [3:0]          awregion_bif;
  wire                awvalid_bif;
  wire                awready_bif;

  // AR Channel: Connections between AR format block and boundary
  wire [3:0]          arid_bif;
  wire [31:0]         araddr_bif;
  wire [7:0]          arlen_bif;
  wire [2:0]          arsize_bif;
  wire [1:0]          arburst_bif;
  wire           arlock_bif;
  wire [3:0]          arcache_bif;
  wire [2:0]          arprot_bif;
  wire [3:0]          arregion_bif;
  wire                arvalid_bif;
  wire                arready_bif;
  // W Channel: Connections between write control block and boundary
  wire                wvalid_bif;
  wire                wready_bif;
  wire [63:0]         wdata_bif;
  wire [7:0]          wstrb_bif;
  wire                wlast_bif;
  // B Channel: Connections between B lookup block and boundary
  wire [3:0]          bid_bif;
  wire [1:0]          bresp_bif;
  wire                bvalid_bif;
  wire                bready_bif;

  // R Channel: Connections between read channel block and boundary
  wire [3:0]          rid_bif;
  wire [1:0]          rresp_bif;
  wire [63:0]         rdata_bif;
  wire                rlast_bif;
  wire                rvalid_bif;
  wire                rready_bif;


  // AXI_fmt
  // AR Channel
  wire                arvalid_fmt;
  wire [31:0]         araddr_fmt;
  wire [7:0]          arlen_fmt;
  wire [2:0]          arsize_fmt;
  wire [1:0]          arburst_fmt;
  wire           arlock_fmt;
  wire [3:0]          arcache_fmt;
  wire [2:0]          arprot_fmt;
  wire [3:0]          arregion_fmt;
  wire [3:0]          arid_fmt;
  wire                arready_fmt;
  // AW Channel
  wire                awvalid_fmt;
  wire [31:0]         awaddr_fmt;
  wire [7:0]          awlen_fmt;
  wire [2:0]          awsize_fmt;
  wire [1:0]          awburst_fmt;
  wire           awlock_fmt;
  wire [3:0]          awcache_fmt;
  wire [2:0]          awprot_fmt;
  wire [3:0]          awregion_fmt;
  wire [3:0]          awid_fmt;
  wire                awready_fmt;

  // AXI_axi_r RIF

  // AR Channel
  wire                arvalid_axi_r;
  wire [31:0]         araddr_axi_r;
  wire [7:0]          arlen_axi_r;
  wire [2:0]          arsize_axi_r;
  wire [1:0]          arburst_axi_r;
  wire           arlock_axi_r;
  wire [3:0]          arcache_axi_r;
  wire [2:0]          arprot_axi_r;
  wire [3:0]          arregion_axi_r;
  wire [3:0]          arid_axi_r;
  wire                arready_axi_r;

  // AW Channel
  wire                awvalid_axi_r;
  wire [31:0]         awaddr_axi_r;
  wire [7:0]          awlen_axi_r;
  wire [2:0]          awsize_axi_r;
  wire [1:0]          awburst_axi_r;
  wire           awlock_axi_r;
  wire [3:0]          awcache_axi_r;
  wire [2:0]          awprot_axi_r;
  wire [3:0]          awregion_axi_r;
  wire [3:0]          awid_axi_r;
  wire                awready_axi_r;


  // R Channel
  wire                rvalid_axi_r;
  wire                rlast_axi_r;
  wire [31:0]         rdata_axi_r;
  wire [1:0]          rresp_axi_r;
  wire [3:0]          rid_axi_r;
  wire                rready_axi_r;

  // W Channel
  wire                wvalid_axi_r;
  wire                wlast_axi_r;
  wire [31:0]         wdata_axi_r;
  wire [3:0]          wstrb_axi_r;
  wire                wready_axi_r;

  // B Channel
  wire                bvalid_axi_r;
  wire [1:0]          bresp_axi_r;
  wire [3:0]          bid_axi_r;
  wire                bready_axi_r;

  // ---------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------




  assign aw_fmt_src_data = {
          awid_axi_r,
          awaddr_axi_r[31:0],
          awlen_axi_r,
          awsize_axi_r,
          awburst_axi_r,
          awlock_axi_r,
          awcache_axi_r,
          awregion_axi_r,
          awprot_axi_r};


  assign awvalid_fmt  = awvalid_axi_r;
  assign awready_axi_r = awready_fmt;
  assign aw_fmt_dst_data  = aw_fmt_src_data;


  // expand the concatenated registered values to the master port outputs
  assign {
          awid_fmt,
          awaddr_fmt[31:0],
          awlen_fmt,
          awsize_fmt,
          awburst_fmt,
          awlock_fmt,
          awcache_fmt,
          awregion_fmt,
          awprot_fmt} = aw_fmt_dst_data;

  //------------------------------------------------------------------------------
  // AW Format Block - Formats the AW Channel and send info to the AWFIFO and
  //                  B Channels 
  //------------------------------------------------------------------------------
  nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_wr_addr_fmt_ysyx_rv32 u_axi_write_address_format
  (
    // global interconnect signals
    .aresetn                          (aresetn_s),
    .aclk                             (aclk_s),

    

    //Signals to/from the Bchannel
    .bdata_data                       (bdata_data),
    .bdata_valid                      (bdata_valid),
    .bdata_ready                      (bdata_ready),

    //Signals to the Write Control Block
    .awfmt_valid                      (awdata_valid),
    .awfmt_ready                      (awdata_ready),
    .awfmt_data                       (awdata_data),

    // Slave Port Write Address Channel
    .awid_s                           (awid_fmt),
    .awaddr_s                         (awaddr_fmt),
    .awlen_s                          (awlen_fmt),
    .awsize_s                         (awsize_fmt),
    .awburst_s                        (awburst_fmt),
    .awvalid_s                        (awvalid_fmt),
    .awready_s                        (awready_fmt),
    .awprot_s                         (awprot_fmt),
    .awcache_s                        (awcache_fmt),
    .awlock_s                         (awlock_fmt),

    // Master Port Write Address Channel
    .awid_m                           (awid_bif),
    .awaddr_m                         (awaddr_bif),
    .awlen_m                          (awlen_bif),
    .awsize_m                         (awsize_bif),
    .awburst_m                        (awburst_bif),
    .awvalid_m                        (awvalid_bif),
    .awready_m                        (awready_bif),
    .awprot_m                         (awprot_bif),
    .awlock_m                         (awlock_bif),
    .awcache_m                        (awcache_bif)
  );
  
  
  assign awregion_bif = awregion_fmt;

  //------------------------------------------------------------------------------
  // Write Control - Controls the merge buffer and pushes to the wfifo/W Channel
  //------------------------------------------------------------------------------

nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_wr_cntrl_ysyx_rv32 u_upsize_axi_write_control
  (
    // global interconnect signals
    .aresetn                          (aresetn_s),
    .aclk                             (aclk_s),

    //Signals to/from the AW format block
    .awfifo_valid                     (awdata_valid),
    .awfifo_ready                     (awdata_ready),
    .awfifo_data                      (awdata_data),

    // Slave Port Write  Channel
    .wvalid_s                         (wvalid_axi_r),
    .wready_s                         (wready_axi_r),
    .wlast                            (wlast_axi_r),

    // Merge buffer Contol signals
    .merge                            (merge),
    .merge_clear                      (merge_clear),
    .data_select                      (data_select),
    .strb_skid_valid                  (strb_skid_valid),

    //Data from merge buffer
    .wdata_merged                     (wdata_merged),
    .wstrb_merged                     (wstrb_merged),

    // Master Port Write  Channel
    .wvalid_m                         (wvalid_bif),
    .wready_m                         (wready_bif),
    .wlast_m                          (wlast_bif),
    .wdata_m                          (wdata_bif),
    .wstrb_m                          (wstrb_bif)
  );


  //------------------------------------------------------------------------------
  // Merge Buffer - Merges data on the Slave W Channel and passes it to the WFIFO
  //------------------------------------------------------------------------------

  nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_wr_merge_buffer_ysyx_rv32 u_upsize_axi_write_merge_buffer
  (
    // global interconnect signals
    .aresetn                          (aresetn_s),
    .aclk                             (aclk_s),

    // outputs
    .wdata_out                        (wdata_merged),
    .wstrb_out                        (wstrb_merged),

    //Inputs
    .wdata_in                         (wdata_axi_r),
    .wstrb_in                         (wstrb_axi_r),

    //Control Signals
    .data_select                      (data_select),
    .merge_skid_valid                 (strb_skid_valid),
    .merge                            (merge),
    .merge_clear                      (merge_clear)
  );



//------------------------------------------------------------------------------
// B Channel Block - Monitors B Channel and removes
//------------------------------------------------------------------------------
  nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_wr_resp_block_ysyx_rv32 u_upsize_axi_write_response_block
  (

  //System Inputs
  .aclk                               (aclk_s),
  .aresetn                            (aresetn_s),

  //Signals from write Address format Block
  .bchannel_ready                     (bdata_ready),
  .bchannel_valid                     (bdata_valid),
  .bchannel_data                      (bdata_data),

  //Slave B channel Signals
  .bready_s                           (bready_axi_r),
  .bvalid_s                           (bvalid_axi_r),
  .bid_s                              (bid_axi_r),
  .bresp_s                            (bresp_axi_r),

  //Master B channel Signals
  .bresp_m                            (bresp_bif),
  .bid_m                              (bid_bif),
  .bvalid_m                           (bvalid_bif),
  .bready_m                           (bready_bif)

  );


  // the inputs are concatenated to interface to the generic register set
  assign ar_fmt_src_data = {
          arid_axi_r,
          araddr_axi_r[31:0],
          arlen_axi_r,
          arsize_axi_r,
          arburst_axi_r,
          arlock_axi_r,
          arcache_axi_r,
          arregion_axi_r,
          arprot_axi_r};



  assign arvalid_fmt  = arvalid_axi_r;
  assign arready_axi_r = arready_fmt;
  assign ar_fmt_dst_data  = ar_fmt_src_data;


  // expand the concatenated registered values to the master port outputs
  assign {
          arid_fmt,
          araddr_fmt[31:0],
          arlen_fmt,
          arsize_fmt,
          arburst_fmt,
          arlock_fmt,
          arcache_fmt,
          arregion_fmt,
          arprot_fmt} = ar_fmt_dst_data;


  //------------------------------------------------------------------------------
  //  Read Address channel coding
  //------------------------------------------------------------------------------

  nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_rd_addr_fmt_ysyx_rv32 u_axi_read_address_format
  (
    // global interconnect signals
    .aresetn                          (aresetn_s),
    .aclk                             (aclk_s),

    //Signals to the ARfifo
    .ardata_valid                     (arfifo_valid),
    .ardata_ready                     (arfifo_ready),
    .ardata_data                      (arfifo_data),

    // Slave Port Write Address Channel
    .arid_s                           (arid_fmt),
    .araddr_s                         (araddr_fmt),
    .arlen_s                          (arlen_fmt),
    .arsize_s                         (arsize_fmt),
    .arburst_s                        (arburst_fmt),
    .arvalid_s                        (arvalid_fmt),
    .arready_s                        (arready_fmt),
    .arprot_s                         (arprot_fmt),
    .arcache_s                        (arcache_fmt),
    .arlock_s                         (arlock_fmt),

    // Master Port Write Address Channel
    .arid_m                           (arid_bif),
    .araddr_m                         (araddr_bif),
    .arlen_m                          (arlen_bif),
    .arsize_m                         (arsize_bif),
    .arburst_m                        (arburst_bif),
    .arvalid_m                        (arvalid_bif),
    .arready_m                        (arready_bif),
    .arprot_m                         (arprot_bif),
    .arlock_m                         (arlock_bif),
    .arcache_m                        (arcache_bif)
  );

  assign arregion_bif = arregion_fmt;

  //------------------------------------------------------------------------------
  //  Read Channel - Demuxes the appropriate data onto the Slave READ bus
  //------------------------------------------------------------------------------

  nic400_ib_chiplink_slv_axi4_tpv_ib_upsize_rd_chan_ysyx_rv32 u_upsize_axi_read_channel
  (

  // global interconnect signals
  .aresetn                           (aresetn_s),
  .aclk                              (aclk_s),

  //Signals from the AR Format Block
  .archannel_data                    (arfifo_data),
  .archannel_valid                   (arfifo_valid),
  .archannel_ready                   (arfifo_ready),

  //RChannel Slave Side Outputs
  .rvalid_s                          (rvalid_axi_r),
  .rdata_s                           (rdata_axi_r),
  .rlast_s                           (rlast_axi_r),
  .rid_s                             (rid_axi_r),
  .rresp_s                           (rresp_axi_r),

  //RChannel Slave Side Inputs
  .rready_s                          (rready_axi_r),

  //RChannel Boundary Side Inputs
  .rvalid_m                          (rvalid_bif),
  .rdata_m                           (rdata_bif),
  .rlast_m                           (rlast_bif),
  .rid_m                             (rid_bif),
  .rresp_m                           (rresp_bif),
  //RChannel Boundary Side Outputs
  .rready_m                          (rready_bif)

  );



  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  // AW Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign aw_boundary_src_data = {
          awid_bif,
          awaddr_bif,
          awlen_bif,
          awsize_bif,
          awburst_bif,
          awlock_bif,
          awcache_bif,
          awregion_bif,
          awprot_bif};


  assign aw_boundary_src_valid = awvalid_bif;
  assign awready_bif = aw_boundary_src_ready;

  assign aw_data_async = aw_boundary_dst_data;
  
  // ---------------------------------------------------------------------------
  // AR Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign ar_boundary_src_data = {
          arid_bif,
          araddr_bif,
          arlen_bif,
          arsize_bif,
          arburst_bif,
          arlock_bif,
          arcache_bif,
          arregion_bif,
          arprot_bif};


  assign ar_boundary_src_valid = arvalid_bif;
  assign arready_bif = ar_boundary_src_ready;

  assign ar_data_async = ar_boundary_dst_data;
  
  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_boundary_src_data = {
          wdata_bif,
          wstrb_bif,
          wlast_bif};


  assign w_boundary_src_valid = wvalid_bif;
  assign wready_bif = w_boundary_src_ready;

  assign w_data_async = w_boundary_dst_data;
  

  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the master port outputs
  assign {
          rid_bif,
          rdata_bif,
          rresp_bif,
          rlast_bif} = r_boundary_dst_data;

  assign r_boundary_dst_ready = rready_bif;
  assign rvalid_bif = r_boundary_dst_valid;




  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the master port outputs
  assign {
          bid_bif,
          bresp_bif} = b_boundary_dst_data;

  assign b_boundary_dst_ready = bready_bif;
  assign bvalid_bif = b_boundary_dst_valid;




  // ---------------------------------------------------------------------------
  // AW Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign aw_slave_port_src_data = {
          awid_axi4_s,
          awaddr_axi4_s[31:0],
          awlen_axi4_s,
          awsize_axi4_s,
          awburst_axi4_s,
          awlock_axi4_s,
          awcache_axi4_s,
          awregion_axi4_s,
          awprot_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          awid_axi_r,
          awaddr_axi_r[31:0],
          awlen_axi_r,
          awsize_axi_r,
          awburst_axi_r,
          awlock_axi_r,
          awcache_axi_r,
          awregion_axi_r,
          awprot_axi_r} = aw_slave_port_dst_data;


  assign awvalid_axi_r = aw_slave_port_dst_valid;
  assign aw_slave_port_dst_ready = awready_axi_r;

  assign aw_slave_port_src_valid = awvalid_axi4_s;
  assign awready_axi4_s = aw_slave_port_src_ready;


  // ---------------------------------------------------------------------------
  // AR Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign ar_slave_port_src_data = {
          arid_axi4_s,
          araddr_axi4_s[31:0],
          arlen_axi4_s,
          arsize_axi4_s,
          arburst_axi4_s,
          arlock_axi4_s,
          arcache_axi4_s,
          arregion_axi4_s,
          arprot_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          arid_axi_r,
          araddr_axi_r[31:0],
          arlen_axi_r,
          arsize_axi_r,
          arburst_axi_r,
          arlock_axi_r,
          arcache_axi_r,
          arregion_axi_r,
          arprot_axi_r} = ar_slave_port_dst_data;


  assign arvalid_axi_r = ar_slave_port_dst_valid;
  assign ar_slave_port_dst_ready = arready_axi_r;

  assign ar_slave_port_src_valid = arvalid_axi4_s;
  assign arready_axi4_s = ar_slave_port_src_ready;


  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at slave_port
  // No register specified for R Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign r_slave_port_src_data = {
          rid_axi_r,
          rdata_axi_r,
          rresp_axi_r,
          rlast_axi_r};

  // expand the concatenated registered values to the master port outputs
  assign {
          rid_axi4_s,
          rdata_axi4_s,
          rresp_axi4_s,
          rlast_axi4_s} = r_slave_port_dst_data;


  assign r_slave_port_dst_data = r_slave_port_src_data;

  assign rvalid_axi4_s = rvalid_axi_r;
  assign rready_axi_r = rready_axi4_s;


  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at slave_port
  // No register specified for W Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_slave_port_src_data = {
          wdata_axi4_s,
          wstrb_axi4_s,
          wlast_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          wdata_axi_r,
          wstrb_axi_r,
          wlast_axi_r} = w_slave_port_dst_data;


  assign w_slave_port_dst_data = w_slave_port_src_data;

  assign wvalid_axi_r = wvalid_axi4_s;
  assign wready_axi4_s = wready_axi_r;


  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at slave_port
  // No register specified for B Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign b_slave_port_src_data = {
          bid_axi_r,
          bresp_axi_r};

  // expand the concatenated registered values to the master port outputs
  assign {
          bid_axi4_s,
          bresp_axi4_s} = b_slave_port_dst_data;


  assign b_slave_port_dst_data = b_slave_port_src_data;

  assign bvalid_axi4_s = bvalid_axi_r;
  assign bready_axi_r = bready_axi4_s;

  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------
  //  AW Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_aw_fifo_wr_ysyx_rv32
  u_aw_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_s),
     .wclk                  (aclk_s),
     // inputs
     .src_valid             (aw_boundary_src_valid),
     .src_data              (aw_boundary_src_data),
     .rpntr_gry_async       (aw_rpntr_gry_async),
     .rpntr_bin             (aw_rpntr_bin),

     // outputs
     .src_ready             (aw_boundary_src_ready),
     .dst_data              (aw_boundary_dst_data),
     .wpntr_gry_async       (aw_wpntr_gry_async)
     );



  //  AR Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_ar_fifo_wr_ysyx_rv32
  u_ar_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_s),
     .wclk                  (aclk_s),
     // inputs
     .src_valid             (ar_boundary_src_valid),
     .src_data              (ar_boundary_src_data),
     .rpntr_gry_async       (ar_rpntr_gry_async),
     .rpntr_bin             (ar_rpntr_bin),

     // outputs
     .src_ready             (ar_boundary_src_ready),
     .dst_data              (ar_boundary_dst_data),
     .wpntr_gry_async       (ar_wpntr_gry_async)
     );



  //  R Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 71
  nic400_ib_chiplink_slv_axi4_tpv_ib_r_fifo_rd_ysyx_rv32
  u_r_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_s),
     .rclk                  (aclk_s),
     // inputs
     .src_data              (r_data_async),
     .dst_ready             (r_boundary_dst_ready),
     .wpntr_gry_async       (r_wpntr_gry_async),

     // outputs
     .dst_data              (r_boundary_dst_data),
     .dst_valid             (r_boundary_dst_valid),
     .rpntr_gry_async       (r_rpntr_gry_async),
     .rpntr_bin             (r_rpntr_bin)
     );



  //  W Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 73
  nic400_ib_chiplink_slv_axi4_tpv_ib_w_fifo_wr_ysyx_rv32
  u_w_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_s),
     .wclk                  (aclk_s),
     // inputs
     .src_valid             (w_boundary_src_valid),
     .src_data              (w_boundary_src_data),
     .rpntr_gry_async       (w_rpntr_gry_async),
     .rpntr_bin             (w_rpntr_bin),

     // outputs
     .src_ready             (w_boundary_src_ready),
     .dst_data              (w_boundary_dst_data),
     .wpntr_gry_async       (w_wpntr_gry_async)
     );



  //  B Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 6
  nic400_ib_chiplink_slv_axi4_tpv_ib_b_fifo_rd_ysyx_rv32
  u_b_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_s),
     .rclk                  (aclk_s),
     // inputs
     .src_data              (b_data_async),
     .dst_ready             (b_boundary_dst_ready),
     .wpntr_gry_async       (b_wpntr_gry_async),

     // outputs
     .dst_data              (b_boundary_dst_data),
     .dst_valid             (b_boundary_dst_valid),
     .rpntr_gry_async       (b_rpntr_gry_async),
     .rpntr_bin             (b_rpntr_bin)
     );



  //  AW Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       61  // Payload Width
     )
  u_aw_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn_s),
     .aclk                  (aclk_s),
     // inputs
     .src_valid             (aw_slave_port_src_valid),
     .src_data              (aw_slave_port_src_data),
     .dst_ready             (aw_slave_port_dst_ready),

     // outputs
     .src_ready             (aw_slave_port_src_ready),
     .dst_data              (aw_slave_port_dst_data),
     .dst_valid             (aw_slave_port_dst_valid)
     );



  //  AR Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 61
  nic400_ib_chiplink_slv_axi4_tpv_ib_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       61  // Payload Width
     )
  u_ar_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn_s),
     .aclk                  (aclk_s),
     // inputs
     .src_valid             (ar_slave_port_src_valid),
     .src_data              (ar_slave_port_src_data),
     .dst_ready             (ar_slave_port_dst_ready),

     // outputs
     .src_ready             (ar_slave_port_src_ready),
     .dst_data              (ar_slave_port_dst_data),
     .dst_valid             (ar_slave_port_dst_valid)
     );



  // R channel is set to wires at slave_port.
    
  // W channel is set to wires at slave_port.
    
  // B channel is set to wires at slave_port.
    

  // ---------------------------------------------------------------------------

//------------------------------------------------------------------------------
// OVL Assertions
//------------------------------------------------------------------------------
// synopsys translate_off

`ifdef ARM_ASSERT_ON
`include "std_ovl_defines.h"



   
`endif
// synopsys translate_on

endmodule

`include "nic400_ib_chiplink_slv_axi4_tpv_ib_undefs_ysyx_rv32.v"
`include "Axi_undefs.v"



// --================================= End ===================================--
